module PC_Register(iPC, oPC, iPCWrite, iReset, iClk);
	input [31:0] iPC;
	input iPCWrite, iReset, iClk;
	output [31:0] oPC;
	reg [31:0] oPC;

	always @(posedge iReset or posedge iClk)
	begin
		if(iReset)
			oPC <= 32'b0;
		else if(iPCWrite)
			oPC <= iPC;
		else
			oPC <= oPC;
	end
	
endmodule